1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of planarizing an interlayer insulating film for a multilayer wiring structure.
2. Description of the Related Art
In the fabrication of a semiconductor device, a multilayer wiring structure has been conventionally formed as disclosed, for example, in Japanese Patent Laid Open No. S64-47053.
Namely, as shown in FIG. 1a, a first layer wiring 55 including an Al--Si alloy is formed on a semiconductor substrate 51. Next, as shown in FIG. 1b, a 200 nm-thick first insulating film 58 consisting of phosphosilicate glass (PSG) is formed on the entire surface by CVD method. Subsequently, a glass solution is spin coated at 5000 rpm, and the coating film is solidified by baking it for 1 min at 150.degree. C. and for 30 min at 300.degree. C. By repeating the spin coating and the baking of the glass solution for two or three times, a glass coating film 510 having a thickness of about 200 nm is formed on the wiring 55 as shown in FIG. 1c. Then, the whole surface of glass coating film 510 is etched all over the surface by 200 nm by reactive ion etching as shown in FIG. 1d. Next, as shown in FIG. 1e, a second insulating film 511 of PSG is formed to a thickness of 400 nm by CVD method. Subsequently, after forming a through hole 512 as shown in FIG. 1f, a two-layer wiring structure is formed by forming a second layer wiring 516 as shown in FIG. 1g.
In addition, in Japanese Patent Laid Open No. S63-21850 there is disclosed the formation of a planarized interlayer insulating film by a method in which a semiconductor substrate is immersed in a solution of material for the formation of a glass coating film or a polyimide film, as will be described in the following. Namely, as shown in FIGS. 2a and 2b, gate electrodes 65 are formed by etching a gate electrode film 64 using a photoresist film 67 as a mask. Next, a planarizing insulating film 610 is formed by immersing the etched gate electrode 65 together with the photoresist film 67 in a solution of material for forming glass coating film or a polyimide film, a so-called "SOG" (spin on glass) or the like as shown in FIG. 2c, and the substrate is subjected to a heat treatment. Further, after removal of the photoresist film as shown in FIG. 2d, a PSG or boron doped phosphosilicate glass (BPSG) insulating film 611 is deposited by, for example, a CVD method, then the film is subjected to a heat treatment. This achieves planarization of the interlayer insulating film.
However, the above-mentioned methods have the following problems. In the first mentioned method, in the isotropic etching process following the formation of the glass coating film, the glass coating film undergoes more etching than the PSG film 58 formed by the CVD method because the etching rate of the glass coating film 510 is higher compared with the same of PSG film 58, which deteriorates the flatness of the surface. Moreover, the thickness of the glass coating film above the wiring 55 depends on the width of the wiring 55. The thicker glass coating film on wider portions of the wiring pattern may not be fully etched even the glass coating film on a narrower portion of the wiring pattern is completely removed by the isotropic etching. When a second layer wiring is subsequently formed after formation of through holes, electric continuity may become lost due to oxidation of the surface of the lower wiring at the bottom of the through holes by the release of contained moisture or hygroscopic moisture in the glass coating film. These defects conspicuously spoil the production yield and the reliability of the semiconductor devices. Furthermore, due to the fact that sufficient flatness cannot be obtained even if planarization is attempted, control of the size of the photoresist pattern for the formation of the upper layer wiring becomes difficult, preventing formation of fine wirings.
In the second mentioned method, the following problems exist. First, because of the formation of a film on the photoresist film by the immersion of the substrate in a solution of material for the purpose of forming an SOG or a polyimide film, this method has a fatal defect that the photoresist film cannot easily be removed in a later step. Moreover, an ordinary SOG film has the drawback that cracks form in the SOG film when a film with thickness greater than 0.2 .mu.m is formed, precluding the possibility of putting such a film to practical use. Furthermore, a heat treatment is required after immersion of the sample in the solution material for formation of the SOG film, but heat treatment at a temperature higher than 150.degree. C. is not feasible because of the presence of the photoresist film. Insufficient heat treatment at low temperature causes the SOG film to melt when the photoresist film is subsequently removed and planarization is deteriorated.
A technique for forming a compact SOG film at low temperature has been proposed in Japanese Patent Application No. H3-234238 (Patent No. 05-74747), No. H3-242239 (Patent No. 05-82512) and No. H3-250781 (Patent No. 05-90249), according to which a SOG film is exposed to a fluoroalkoxysilane or a fluoroalkoxymetal containing vapor to accelerate condensation and polymerization reactions for formation of the SOG film.